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Cadence LDV V3.3 for Win32 英文光碟正式版




破解說明:請詳閱光碟\CRACK\目錄下的Readme.TXT



軟體簡介:

Cadence LDV V3.3 for Win32 英文光碟正式版


Cadence LDV V3.3是一套可以跨平台的機械模擬測試軟體，最主要是可以測試當你
的程式要在自動化控制機器上執行時，是否會遇到什麼問題，它可以在第一時間就
完成測試，所以你的程式可以更加穩定，而且它所附的工具程式可以幫助你更方便
的除錯，這在一般的自動化控制機器上要達到是非常困難的。在WIN32 平台上只有
兩個模SimVision 及Vorilog-XL其餘的模組只有在Unix版本才有支援。至於Sun 或
是Linux平台的版本，已列入發展計劃了，但是你可能要稍微的等等了!!

Cadence LDV is Logic Design and Verification Bundle for EDA.
With Cadence ldv, EDA engineer can do simulation at behavior level using
Verilog-XL,NC-Verilog or NC-VHDL. You can browse your resource, domostrate
and compare waves quickly and browse signal stream. Also, there are code
management tools like VeriSure and VHDL Cover and so on which can be used
to analyze result of simulation. Then u can also do simulation at gate
level using Buldgates. Verifault XL,another tool in the Bundle,can be used
to dofault analyzation.

Notes: This is windows version 3.3, Cadence has removed many function
from the bundle. It only includes SimVision and Verilog-XL. Bundle with
full function can be found in unix version. So pls waiting for our
Linux/Sun rls.;-)